Phase-locked loops (PLLs) are commonly used in digital data processing systems, particularly single-chip microprocessors, for the generation of internal (on-chip) clock signals from an external (off-chip) reference clock. In general, PLL-based clock generators are designed using voltage controlled oscillators (VCO). For example, in U.S. Pat. No. 4,494,021, the VCO is comprised of a recirculating delay line, wherein the delay per stage is varied in proportion to the relationship between the frequencies of the control and controlled signals. In "Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 2, Pages 255-261, April 1987, a similar ring oscillator VCO, provided with taps between successive delay stages, is used to generate nonoverlapping clock phases of a system clock. However, since such VCO's are essentially analog in nature, integration with digital circuitry requires a significantly more complex and expensive manufacturing process. It would be of significant benefit if a PLL could be constructed entirely of digital components.